The present invention relates generally to the field of memory devices and in particular to a concurrent read of status information from two or more memory devices.
Portable electronic devices have become ubiquitous accoutrements to modern life. Two relentless trends in portable electronic devices are increased functionality and decreased size. Increased functionality demands higher computing power and more memory. The decreasing size of portable electronic devices places a premium on power consumption, as smaller batteries can store and deliver less power. Thus, advances that increase performance and decrease power consumption are advantageous in general, and in particular for portable electronic devices.
Most portable electronic devices include some form of Dynamic Random Access Memory (DRAM) to store instructions and data for a processor or other controller. DRAM is the most cost-effective solid-state memory technology available. Synchronous DRAM (SDRAM) offers both improved performance and simplified interface design over conventional DRAM by aligning all control signals and data transfer cycles to clock edges. Double data rate (DDR) SDRAM allows data transfers on both rising and falling edges of the clock, providing still higher performance.
A basic aspect of all DRAM operation is that the capacitive charge storing data at each bit position must be periodically renewed to preserve the data state. The DRAM array is refreshed by row; some SDRAM devices may refresh the same row in multiple DRAM banks at the same time. Each row in the DRAM array must be refreshed within a specified refresh period. The DRAM rows may be refreshed sequentially once per refresh period, known as a burst refresh. However, this prevents access to the DRAM array for the time necessary to cycle through all of the rows, and imposes a significant performance degradation. Alternatively, refresh cycles directed to each row may be spread evenly throughout the refresh period, interspersed with read and write data transfers. This is known as distributed refresh. Distributed refresh is more commonly implemented, as it imposes less of a performance penalty.
Co-pending U.S. patent application “Directed Autorefresh Synchronization,” Ser. No. 11/115,915, filed on Apr. 27, 2004, and assigned to the assignee of the present invention, is incorporated herein by reference in its entirety. This application discloses an auto-refresh option, wherein a refresh row counter is maintained in the SDRAM device. In auto-refresh mode, a memory controller such as a processor must supply only periodic refresh commands; the SDRAM device takes care of sequencing refresh row addresses. Whether in a traditional refresh mode (when the processor must provide refresh row addresses) or in an auto-refresh mode, the timing of the refresh command is determined by the memory controller.
The total required refresh period, and hence the spacing of refresh cycles in a distributed refresh operation, depends on the temperature of the DRAM array die. As a general rule of thumb, the refresh rate must be doubled for every 10° C. increase in the DRAM array die temperature. The refresh period specified for a SDRAM device is typically that required by the DRAM at its highest anticipated operation temperature. Thus, whenever the DRAM array die is at a lower temperature, the refresh period is longer, and the distributed refresh cycles may be spaced further apart, thus reducing their impact on DRAM read and write accesses. This would both improve processor performance and reduce power consumption by eliminating unnecessary refresh activity.
Co-pending U.S. patent application “Register Read for Volatile Memory,” Ser. No. 11/128,829, filed on May 13, 2005, and assigned to the assignee of the present invention, is incorporated herein by reference in its entirety. This patent application discloses a SDRAM device having a temperature sensor, and defines a Status Register Read (SRR) operation that resembles a data read operation in timing and operation, to read the temperature sensor output. The SRR command is defined herein as a Mode Register Set (MRS) command with the bank select lines driven to 2′b10, followed by a READ command. The address bits during the MRS command select the status information to be read. For example, in one embodiment, SDRAM die temperature information may be read by driving all address bits to 0x0 during the MRS command. Other status information (e.g., the contents of the mode or extended mode registers, ID information, and the like) may be mapped to other addresses.
The SRR command may accesses information associated with the temperature of the DRAM die. This information may comprise the actual temperature of the die, the uncalibrated output value of a temperature sensor, the minimum refresh rate required for the current temperature, a refresh rate multiplier based on the current temperature, or other temperature-related information from which the controller may ascertain the required refresh rate. As used herein, all such information is referred to as temperature information, and is distinct from any data stored in the DRAM array.
Using the SRR operation, a memory controller, such as a processor, may periodically read the output of the temperature sensor and calculate the actual minimum required refresh rate. During transient thermal conditions, such as on initial power-up or when “waking” from a battery power-saving “sleep” mode, the controller may read the temperature sensor relatively often, such as every four to six microseconds, to dynamically optimize the refresh rate. When the DRAM die temperature stabilizes, the controller may reduce the frequency of status register read operations, to devote greater bus bandwidth to memory access and refresh operations. Because the SRR operation timings are similar to those of READ operations to data in the DRAM array, SRR operations may be integrated into regular memory accesses.
Sequentially reading status information, such as temperature, separately from each DRAM device in each memory subsystem rank (i.e., each DRAM device tied to the same chip select signal) consumes available memory bandwidth that could otherwise be used to perform pending memory accesses to read, write, and refresh the memory array. Reducing the number of SRR operations would improve memory system performance, and would reduce power consumption by requiring fewer memory accesses.